The transistor is the fundamental building block for electronic circuit design. Performance metrics, like speed, power consumption and the number of transistors used are directly related to the choice of transistor technology that is used for the implementation. The selected technology may hence strongly influence the circuit performance.
The main factors that define a field-effect transistor (FET) are the type of carriers used (n or p) and the threshold voltage. The type of carriers determines the response of an input voltage to the gate on the output current at the drain terminal. For a n-type device the on-current is increased as the gate voltage is increased, while for a p-type device the on-current is decreased as the gate voltage is increased. The type of conduction is set by the doping of the material. The threshold voltage determines the voltage level at which the transistor goes from the off-state to the on-state. In a planar technology the threshold voltage is given by the geometry of the device. Normally-on (or depletion mode) DFETs often have advantageous high-frequency performance as compared to normally-off (or enhancement mode) EFETs, since the channel in DFETs remains open on the source and drain side of the gate, which reduces the access resistance. EFETs often suffer from high access resistance as the external part of the channel remains partially depleted which adds resistance. It is hence well known in the field that it is difficult to design and fabricate good enhancement mode devices.
While circuits may be designed with one type of transistors only, it is often favorably to combine different types of transistors. For instance, in the complementary-metal-oxide-semiconductor technology (CMOS) n- and p-type metal-oxide-semiconductor field-effect transistors MOSFETs, are combined primarily to reduce the power consumption in logic elements. Notably, the CMOS does only consume negligible static power while the dynamic power consumption is dominating. The price to pay for this implementation is that the speed is set by the comparably slower PMOS transistors.
The main advantage of using semiconductors commonly referred to as III/V semiconductors is the carrier transport properties. n-type devices are typically considered mainly due to the substantially higher mobility for the electrons than for the holes. In III/V-design, where there is a lack of CMOS technology, design with DFETs only may be considered and has been demonstrated for instance in the unbuffered FET logic circuits and in Schottky diode FET logic circuits. These circuits, however, require level shifters for the switching between negative and positive biases and may even require two levels of signals in the circuit. This adds complexity to the circuit and increases the power consumption. Design with EFETs only is more advantageous, since the fact that the transistor is normally off reduces the static power consumption as compared to the DFET design. The drawback lies in the comparably lower speed of the EFET. In many applications, it is, however, desired to utilize both EFETs and DFETs and use the alternating threshold voltage to switch the conductivity between a pair of transistors, as employed in the directly coupled field effect logic (DCFL) circuits. These circuits have demonstrated record low-power and high-speed operation. The limitations in the planar technology are related to the mentioned difficulties in making EFETs with low access resistance, the difficulty to control the threshold voltage in the post-growth process, the presence of short-channel effects as the planar gate length is reduced, and the lack of suitable substrate and lattice-matched heterostructure material for the narrow band gap technologies.